The present invention relates to a differential output buffer composed of a current mode logic (CML) circuit.
FIG. 3 is a circuit diagram illustrating an example of a configuration of a conventional differential output buffer. A differential output buffer 30 illustrated in FIG. 3 is provided with a differential output circuit 12, and a bias voltage generation circuit 34 that generates a bias voltage for controlling a current flowing in the differential output circuit 12.
The differential output circuit 12 is a CML circuit that outputs a differential output signal corresponding to a differential input signal, and is provided with a first switch 16a and a second switch 16b, a first internal resistor 18a and a second internal resistor 18b, a first current source 20a, a first external capacitor 22a and a second external capacitor 22b, and a first external resistor 24a and a second external resistor 24b. 
FIG. 3 illustrates the case in which a high voltage and a low voltage are input as the differential input signal to a gate of an NMOS (N-type MOS transistor) constituting the first switch 16a and a gate of an NMOS constituting the second switch 16b, respectively, and thus, the first switch 16a is in an ON state, and the second switch 16b is in an OFF state.
The differential output signal of the differential output circuit 12 is output from a first internal node between the first internal resistor 18a and the first switch 16a, and a second internal node between the second internal resistor 18b and the second switch 16b. 
The bias voltage generation circuit 34 is provided with a second current source 36, and a constant current generation circuit 38. An NMOS constituting the second current source 36 is configured with an NMOS having a size of “1/a” times the size of the first current source 20a (“a” is a positive real number other than zero).
Next, an operation of the differential output buffer 30 will be described.
Here, the resistance values of the first internal resistor 18a and the second internal resistor 18b are each represented as RINT, the resistance values of the first external resistor 24a and the second external resistor 24b are each represented as REXT, the currents flowing in the first internal resistor 18a and the second internal resistor 18b are respectively represented as IA and IB, the voltages of the first internal node and the second internal node are respectively represented as VA and VB, and currents flowing through the first current source 20a and the second current source 36 are respectively represented as ITOTAL and ISOURCE.
As illustrated in FIG. 3, when a high voltage and a low voltage are respectively input as the differential input signal to the gate of the NMOS of the first switch 16a and the gate of the NMOS of the second switch 16b, the first switch 16a of the differential output circuit 12 is in an ON state and the second switch 16b thereof is in an OFF state.
In this case, the current IA flows from a high voltage power supply through the first internal resistor 18a while the current IB flows from the high voltage power supply through the second internal resistor 18b, the second external capacitor 22b, the second external resistor 24b, the first external resistor 24a, and the first external capacitor 22a, and the current ITOTAL that is a sum of the two currents flows to a low voltage power supply through the first switch 16a and the first current source 20a. As a result, the differential output signal with the first internal node at a low voltage and the second internal node at a high voltage is output.
In the bias voltage generation circuit 34, the constant current ISOURCE supplied from the constant current generation circuit 38 flows to a low voltage power supply through the second current source 36. Since the NMOS of the first current source 20a and the NMOS of the second current source 36 constitute a current mirror circuit, the current ITOTAL that has a volume of “a” times the volume of the current ISOURCE flowing through the second current source 36 flows through the first current source 20a. 
The voltage VA and the voltage VB, that is, differential amplitude VOD=VA−VD is determined according to the current value of the current ITOTAL, the resistance value RINT, and the resistance value REXT.
Here, in the conventional differential output buffer 30, there is a problem in that the differential amplitude VA−VB varies. The causes of occurrence of the variation in the differential amplitude VA−VB are the following factors of (1) and (2):
(1) Mismatch of a source-drain voltage VDS between the NMOS of the first current source 20a and the NMOS of the second current source 36, which constitute the current mirror circuit; and
(2) Variation in the resistance value RINT of the first internal resistor 18a and the second internal resistor 18b. 
Regarding (1), if the channel length (L length) of the transistor is increased in order to reduce the influence of the mismatch of the voltage VDS, the variation in the current ITOTAL, that is, the variation in the differential amplitude VA−VB can be decreased to some extent, but the size increases.
Regarding (2), since the current ISOURCE flowing through the second current source 36 of the mirror source of the current mirror circuit is generated by the on-resistance of the NMOS of the second current source 36, the current increases or decreases, for example, according to the variation in the resistance value RINT of the first internal resistor 18a and the second internal resistor 18b formed on a semiconductor chip, and thus the differential amplitude VA−VB varies. Meanwhile, the resistance value REXT of the first external resistor 24a and the second external resistor 24b connected to the outside of the semiconductor chip hardly varies, which does not accord with the variation in the resistance value RINT of the first internal resistor 18a and the second internal resistor 18b. 
Then, the degree of influence of the variation in the resistance value RINT of the first internal resistor 18a and the second internal resistor 18b on the differential amplitude VA−VB of the differential output signal is calculated as follows.
Since the current ITOTAL is a sum of the current IA and the current IB, the current ITOTAL is expressed by Equation (1).ITOTAL=IA+IB  Equation (1)
The current values of the current IA and the current IB are expressed by Equations (2) and (3).
                              I          A                =                                                            R                INT                            +                              2                ⁢                                                                  ⁢                                  R                  EXT                                                                                    2                ⁢                                                                  ⁢                                  R                  INT                                            +                              2                ⁢                                                                  ⁢                                  R                  EXT                                                              ·                      I            TOTAL                                              Equation        ⁢                                  ⁢                  (          2          )                                                  I          B                =                                            R              INT                                                      2                ⁢                                                                  ⁢                                  R                  INT                                            +                              2                ⁢                                                                  ⁢                                  R                  EXT                                                              ·                      I            TOTAL                                              Equation        ⁢                                  ⁢                  (          3          )                    
Since the voltage VA and the voltage VB are calculated with a product of the current value and the resistance value, the voltage VA and the voltage VB are expressed by Equations (4) and (5) obtained by using Equations (2) and (3).
                              V          A                =                                            I              A                        *                          R              INT                                =                                                                      R                  INT                                +                                  2                  ⁢                                                                          ⁢                                      R                    EXT                                                                                                2                  ⁢                                                                          ⁢                                      R                    INT                                                  +                                  2                  ⁢                                                                          ⁢                                      R                    EXT                                                                        ·                          I              TOTAL                        ·                          R              INT                                                          Equation        ⁢                                  ⁢                  (          4          )                                                  V          B                =                                            I              B                        *                          R              INT                                =                                                    R                INT                                                              2                  ⁢                                                                          ⁢                                      R                    INT                                                  +                                  2                  ⁢                                                                          ⁢                                      R                    EXT                                                                        ·                          I              TOTAL                        ·                          R              INT                                                          Equation        ⁢                                  ⁢                  (          5          )                    
The differential amplitude VA−VB is calculated using Equation (6) from Equations (4) and (5).
                                          V            A                    -                      V            B                          =                                            I              TOTAL                        ·                          R              INT                        ·                          R              EXT                                                          R              INT                        +                          R              EXT                                                          Equation        ⁢                                  ⁢                  (          6          )                    
Thus, in the conventional differential output buffer 30, the terms of the current ITOTAL, the resistance value RINT of the first internal resistor 18a and the second internal resistor 18b, and the resistance value REXT of the first external resistor 24a and the second external resistor 24b are included in the equation of the differential amplitude VA−VB. Therefore, it can be seen that the differential amplitude VA−VB varies according to the variation in the current ITOTAL, that is, the voltage VDS, and also varies according to the variation in the resistance value RINT.
FIG. 4 is an exemplary eye diagram illustrating the differential amplitude VA−VB of the differential output buffer illustrated in FIG. 3. The vertical axis of the eye diagram illustrated in FIG. 4 indicates voltage V (mV), and the horizontal axis indicates time. This eye diagram is for the case in which it is assumed that the resistance value RINT has a variation of ±20% due to a variation in a process. The solid line indicates the case in which there is a variation of −20%, the dashed line indicates the case in which there is no variation, and the long dashed short dashed line indicates the case in which there is a variation of +20%. As shown in this eye diagram, it can be confirmed that, in the conventional differential output buffer 30, the differential amplitude VA−VB greatly varies according to the variation in the resistance value RINT.
Here, prior art documents relevant to the present invention include JP 11-513235 A relating to an analog front-end circuit that converts an input voltage to a differential current, JP 2010-98590 A relating to a differential output buffer that receives an input differential signal, and generates and outputs an output differential signal having a desired center voltage and desired amplitude, JP 11-41085 A relating to an output buffer circuit that complementarily outputs data, JP 2009-225205 A relating to a CML circuit that can suppress a variation in characteristics caused by a variation in a manufacturing process, JP 2006-42349 A relating to a signal level in a current mode logic circuit, and the like.